Performance analysis of a two levels carry-skip adder implemented in complementary pass-transistor logic

Antonio G.M. Strollo, Ettore Napoli

Performance evaluation of a two-level carry-skip adder using complementary pass-transistor logic (CPL) is presented in this paper. The adder is compared with a full custom CMOS version of the two level carry-skip architecture, with a carry-lookahead adder automatically generated with the ALLIANCE CAD tools and with a recently proposed 32 bits carry-select adder. Furthermore, the performances of a single level carry-skip adder implemented in CPL are investigated.

These comparisons are carried-out in order to evaluate the impact of the architecture and of the logic style on the performances.