Antonio G.M. Strollo, Ettore Napoli, Carlo Cimino
abstract
A low power double edge-triggered (DET) flip-flop using a single latch is presented.
In the proposed circuit data is sampled into the latch during a short transparency period for each edge of the clock signal. The proposed flip-flop requires small silicon area and has lower power dissipation with respect to previously reported DET flip-flops.