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DAVIDE DE CARO

 

 

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I work in the area of digital integrated VLSI circuit design, with specific scientific contributions given in the area of digital arithmetic circuits and subsystems (adders, multipliers, linear interpolators, approximate arithmetic), energy efficient digital circuits and techniques (low-power flip-flops, dynamic frequency scaling circuits), low-power 2D/3D GPU subsystems (special function units, logarithmic converters, coordinate conversion processors), digital baseband communications building blocks (digital synthesizers, mixers, FEC decoders, modulator/demodulators) and clock generation aimed to low-power operation and EMI reduction in SoCs.

 

Selected list of publications

1.           D. Esposito, D. De Caro, A.G. M. Strollo, “Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands”, IEEE Trans. on Circuits and Systems I: Regular Papers, vol.63, no.8, pp.1200-1209, Aug.2016.

2.           D. De Caro, F. Tessitore, G. Vai, N. Imperato, N. Petra, E. Napoli, C. Parrella, A.G.M. Strollo, “A 3.3GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28nm CMOS”, IEEE Journal of Solid State Circuits, vol.50, no.9, pp.2074-2089, Sept. 2015.

3.           D. Esposito, D. De Caro, E. Napoli, N. Petra, A.G.M. Strollo, “Variable Latency Speculative Han-Carlson Adder”, IEEE Trans. on Circuits and Systems I: Regular Papers, vol.62, no.5, pp.1353-1361, May 2015.

4.           A. Cilardo, D. De Caro, N. Petra, F. Caserta, N. Mazzocca, E. Napoli, A.G.M. Strollo, “High Speed Speculative Multipliers Based on Speculative Carry-Save Tree”, IEEE Trans. on Circuits and Systems I: Regular Papers, vol.61, no.12, pp.3426-3435, Dec. 2014.

5.           D. De Caro, M. Genovese, E. Napoli, N. Petra, A.G.M. Strollo, “Accurate Fixed-Point Logarithmic Converter”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.61, no.7, pp.526 530, Jul. 2014.

6.           D. De Caro, “Optimal Discontinuous Frequency Modulation for Spread-Spectrum Clocking”, IEEE Trans. on Electromagnetic Compatibility, vol.55, no.5, pp.891-900, Oct. 2013.

7.           D. De Caro, N. Petra, A.G.M. Strollo, F. Tessitore, E. Napoli, “Fixed Width Multipliers and Multipliers-Accumulators with Min-Max Approximation Error”, IEEE Trans. on Circuits and Systems I: Regular Papers, vol.60, no.9, pp.2375-2388, Sept. 2013.

8.           N. Petra, S. Russo, D. De Caro, E. Napoli, G. Barbarino, A.G.M. Strollo, “NORA based TDC in 90nm CMOS”, Microelectronics Journal, vol.44, no.6, pp.489-495, Jun. 2013.

9.           D. De Caro, “Glitch-free NAND-based Digitally Controlled Delay-Lines”, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol.21, no.1, pp.55-66, Jan. 2013.

10.    M. Costagliola, A. Girardi, D. De Caro, R. Izzi, N. Rinaldi, M. Spirito, P. Spirito, “An experimental power-lines model for digital ASICs based on transmission-lines”, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol.20, no.1, pp.162-166, Jan.2012.

11.    S. Russo, N. Petra, D. De Caro, G. Barbarino, A.G.M. Strollo, “A 41 ps ASIC time-to-digital converter for physics experiments”, Nuclear Instruments and Methods in Physics Research Section A, vol.659, no.1, pp.422-427, Dec. 2011.

12.    D. De Caro, N. Petra, A.G.M. Strollo, “Direct Digital Frequency Synthesizer Using Non-Uniform Piecewise-Linear Approximation”, IEEE Trans. on Circuits and Systems I: Regular Papers, vol.58, no.10, pp.2409-2419, Oct. 2011.

13.    D. De Caro, N. Petra, A.G.M. Strollo, “Efficient Logarithmic Converters for Digital Signal Processing Applications”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.58, no.10, pp.667-671, Oct. 2011.

14.    N. Petra, D. De Caro, V. Garofalo, E. Napoli, A.G.M. Strollo, “Design of Fixed-Width Multipliers with Linear Compensation Function”, IEEE Trans. on Circuits and Systems I: Regular Papers, vol.58, no.5, pp.947-960, May 2011.

15.    A.G.M. Strollo, D. De Caro, N. Petra, “Elementary Functions Hardware Implementation Using Constrained Piecewise Polynomial Approximations”, IEEE Transactions on Computers, vol.60, no.3, pp.418-432, Mar. 2011.

16.    N. Petra, D. De Caro, V. Garofalo, E. Napoli, A.G.M. Strollo, “Truncated Binary Multipliers with Variable Correction and Minimum Mean Square Error”, IEEE Trans. on Circuits and Systems I: Regular Papers, vol.57, no.6, pp.1312-1325, Jun. 2010.

17.    D. De Caro, C.A. Romani, N. Petra, A.G.M. Strollo, C. Parrella, “A 1.27GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65nm CMOS”, IEEE Journal of Solid State Circuits, vol.45, no.5, pp.1048-1060, May 2010.

18.    D. De Caro, N. Petra, A.G.M. Strollo, “High Performance Special Function Unit for Programmable 3 D Graphics Processors”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.56, no.9, pp.1968 1978, Sept.2009.

19.    D. De Caro, N. Petra, A.G.M. Strollo, “Digital Synthesizer/Mixer with Hybrid CORDIC Multiplier Architecture: Error Analysis and Optimization”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.56, no.2, pp.364-373, Feb.2009.

20.    A.G.M. Strollo, D. De Caro, N. Petra, “A 430 MHz, 280 mW Processor for the Conversion of Cartesian to Polar Coordinates in 0.25mm CMOS”, IEEE Journal of Solid State Circuits, vol.43, no.11, pp.2503-2513, Nov.2008.

21.    D. De Caro, N. Petra, A.G.M. Strollo, “Reducing Look-up Table Size in Direct Digital Frequency Synthesizers using Optimized Multipartite Table Method”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.55, no.7, pp.2116-2127, Aug.2008.

22.    A. Bonfanti, D. De Caro, A.D. Grasso, S. Pennisi, C. Samori, A.G.M. Strollo, “A 2.5 GHz DDFS PLL with 1.8 MHz bandwidth in 0.35 m CMOS”, IEEE Journal of Solid State Circuits, vol.43, no.6, pp.1403-1413, June 2008.

23.    N. Petra, D. De Caro, A.G.M. Strollo, “A novel Architecture for Galois Fields GF(2m) Multipliers based on Mastrovito Scheme”, IEEE Transactions on Computers, vol.56, no.11, pp.1470-1483, doi: 10.1109/TC.2007.70741, Nov.2007.

24.    A.G.M. Strollo, D. De Caro, N. Petra, “A 630MHz, 76mW, Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique”, IEEE Journal of Solid-State Circuits, vol.42, no.2, pp.350 360, Feb.2007.

25.    D. De Caro, N. Petra, A.G.M. Strollo, “A 380MHz Direct Digital Synthesizer/Mixer with Hybrid CORDIC Architecture in 0.25mm CMOS”, IEEE Journal of Solid-State Circuits, vol.42, no.1, pp.151-160, Jan.2007.

26.    A.G.M. Strollo, D. De Caro, E. Napoli, N.Petra, “A Novel High-Speed Sense Amplifier based Flip-flop”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.13, no.11, pp.1266–1274, Nov.2005.

27.    D. De Caro, A.G.M. Strollo, “High Performance Direct Digital Frequency Synthesizers in 0.25μm CMOS Using Dual-Slope Approximation”, IEEE Journal of Solid-State Circuits, vol.40, no.11, pp.2220-2227, Nov.2005.

28.    A.G.M. Strollo, N. Petra, D. De Caro, “Dual-tree Error Compensation for High Performance Fixed-width Multipliers”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.52, no.8, pp.501-507, Aug. 2005.

29.    D. De Caro, A.G.M. Strollo, “High Performance Direct Digital Frequency Synthesizers Using Piecewise Polynomial Approximation”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.52, no.2, pp.324-337, Feb. 2005.

30.    D. De Caro, E. Napoli, A.G.M. Strollo, “Direct Digital Frequency Synthesizers with Polynomial Hyper-Folding Technique”, IEEE Transactions on Circuits and Systems-II: Express Briefs, vol.51, no.7, pp.337-344, July 2004.

31.    A.G.M. Strollo, D. De Caro, “Booth Folding Encoding for High Performance Squarer Circuits”, IEEE Transaction on Circuits and Systems II: Analog and Digital Signal Processing, vol.50, no.5, pp.250-254, May 2003.

32.    A.G.M. Strollo, E. Napoli, D. De Caro, “Low power flip-flops with reliable clock gating”, Microelectronics Journal, vol.32, no.1, pp.21-28, Jan.2001.

33.    A.G.M. Strollo, D. De Caro, “Low power flip-flop with clock gating on master and slave latches”, Electronics letters, vol.36, no.4, pp.294-295, Feb.2000.

34.    D. De Caro, N. Petra, A.G.M. Strollo, “A 630MHz Direct Digital Frequency Synthesizer with 90dBc SFDR in 0.25mm CMOS”, Proc. of IEEE International Solid-State Circuits Conference 2006, San Francisco, pp.256-257, Feb.2006.

35.    D. De Caro, N. Petra, A.G.M. Strollo, “A 380MHz, 150mW Direct Digital Synthesizer/Mixer in 0.25mm CMOS”, Proc. of IEEE International Solid-State Circuits Conference 2006, San Francisco, pp.258-259, Feb.2006.

36.    A.G.M. Strollo, E. Napoli, D. De Caro, “Direct Digital Frequency Synthesizers using high-order Polynomial Approximation”, IEEE International Solid-State Circuit Conference, San Francisco, pp.134-135, Feb. 4-6 2002.