HtComp

Proposed in July 2013 and officially launched in February 2014, the activities of the HtComp project have already spawned numerous high-impact results in the area of electronic design automation, code-to-code transformation for high-level synthesis, memory optimization, automated design of on-chip interconnect. The results are presented in articles appeared in leading international journals and conferences. Below we list the main publications describing the results of the HtComp project activities:


    Journals
    1. A. Cilardo, L. Gallo, "Improving Multi-Bank Memory Access Parallelism with Lattice-based Partitioning", ACM Transactions on Architecture and Code Optimization, vol. 11, no. 4, 2014
    2. A. Cilardo, E. Fusella, L. Gallo, A. Mazzeo, "Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects", to appear in ACM Transactions on Embedded Systems, 2014.
    3. A. Cilardo, E. Fusella, L. Gallo, A. Mazzeo, N. Mazzocca, "Automated design space exploration for FPGA-based heterogeneous interconnects", in Springer Journal on Design Automation for Embedded Systems, March 2014.
    4. A. Cilardo, D. Socci, N. Mazzocca, "ASP-based Optimized Mapping in a Simulink-to-MPSoC Design Flow", in Elsevier Journal of Systems Architecture, vol. 60, no. 1, pp. 108-118, January 2014.
    5. A. Cilardo, L. Gallo, N. Mazzocca, "Design Space Exploration for High-Level Synthesis of Multi-Threaded Applications", in Elsevier Journal of Systems Architecture, vol. 59, no. 10, pp. 1171-1183, 2013.

    Conferences
    1. A. Cilardo and L. Gallo, "Interplay of loop unrolling and multidimensional memory partitioning in HLS", accepted for presentation at Design, Automation and Test in Europe Conference (DATE15), 2015
    2. E. Fusella, J. Flich, A. Cilardo, A. Mazzeo, "On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs", HiPEAC Workshop on SiPhotonics: Exploiting Silicon Photonics for energy-efficient high-performance computing, Jan. 2015
    3. A. Cilardo, L. Gallo, "Improving Multi-Bank Memory Access Parallelism with Lattice-based Partitioning", in proc. of the 2015 European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC) conference, Jan. 2015
    4. A. Cilardo, E. Fusella, L. Gallo, A. Mazzeo, "Joint Communication Scheduling and Interconnect Synthesis for FPGA-based Many-Core Systems", Proc. of Design, Automation and Test in Europe Conference (DATE'14), 2014
    5. L. Gallo, A. Cilardo, S. Bayliss, D. Thomas, G. Constantinides, "Area Implications of Memory Partitioning for High-Level Synthesis on FPGAs", Proc. of International Conference on Field Programmable Logic and Applications (FPL'14), 2014
    6. A. Cilardo and L. Gallo, "Generating On-Chip Heterogeneous Systems from High-Level Parallel Code", in Procs. of the Euromicro Conference on Digital System Design (DSD), 2014
    7. A. Cilardo, L. Gallo, A. Mazzeo, N. Mazzocca, "Efficient and Scalable OpenMP-based System-Level Design", Proc. of Design, Automation and Test in Europe Conference (DATE13), 2013
    8. A. Cilardo, E. Fusella, L. Gallo, A. Mazzeo, "Automated Synthesis of FPGA-based Heterogeneous Interconnect Topologies", Proc. of International Conference on Field Programmable Logic and Applications (FPL'13), 2013