Peer Reviewed Journal Articles

[j10] E. Fusella & A. Cilardo (2018). Lattice-based Turn Model for Adaptive Routing. IEEE Transactions on Parallel and Distributed Systems (TPDS) , to appear.
[j9] E. Fusella & A. Cilardo (2018). Reducing power consumption of lasers in photonic NoCs through application-specific mapping. ACM Journal on Emerging Technologies in Computing Systems (JETC) , to appear.
[j8] E. Fusella, J. Flich & A. Cilardo (2017). Path setup for hybrid NoC architectures exploiting flooding and standby. IEEE Transactions on Parallel and Distributed Systems (TPDS) , 28(5), 1403-1416.
[j7] E. Fusella & A. Cilardo (2017). H2ONoC: A Hybrid Optical-Electronic NoC Based on Hybrid Topology. IEEE Transactions on Very Large Scale Integration Systems (TVLSI) , 25(1), 330-343.
[j6] E. Fusella & A. Cilardo (2016). Crosstalk-aware automated mapping for optical networks-on-chip. ACM Transactions on Embedded Computing Systems (TECS), 16(1), 16.
[j5] E. Fusella & A. Cilardo (2016). Lighting up on-chip communications with photonics: Design tradeoffs for optical noc architectures. IEEE Circuits and Systems Magazine, 16(3), 4-14.
[j4] E. Fusella & A. Cilardo (2016). Minimizing power loss in optical networks-on-chip through application-specific mapping. Microprocessors and Microsystems, 43, 4-13.
[j3] A. Cilardo & E. Fusella (2016). Design automation for application-specific on-chip interconnects: A survey. Integration, the VLSI Journal, 52, 102-121.
[j2] A. Cilardo, E. Fusella, L. Gallo & A. Mazzeo. (2015). Exploiting concurrency for the automated synthesis of MPSoC interconnects. ACM Transactions on Embedded Computing Systems (TECS), 14(3), 57.
[j1] A. Cilardo, E. Fusella, L. Gallo, A. Mazzeo. & N. Mazzocca (2014). Automated design space exploration for FPGA-based heterogeneous interconnects. Design Automation for Embedded Systems, 18(3-4), 157-170.

Books Chapters

[bc1] E. Fusella, A. Cilardo & J. Flich (2017). Application-Specific Mapping Optimizations for Photonic Networks-on-Chip. in Optical Interconnects for Computing Systems , ed. G. Nicolescu, S. Le Beux, M. Nikdast, J. Xu, River Publishers 2017.

Peer Reviewed Conference Papers

[c9] E. Fusella & A. Cilardo (2018, March). Understanding Turns Models for Adaptive Routing: the Modular Approach. To be presented at Design, Automation and Test in Europe Conference (DATE'18)
[c8] J. Flich, A. Cilardo, M. Kovac, R. Tornero, M. Gagliardi, E. Fusella, J.M. Martinez & T. Picornell (2017). Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration. To appear in International Conference on Parallel Computing (ParCo).
[c7] E. Fusella (2017, March). A deterministic approach to improve inter-domain parallelism of clustered MPSoC Interconnects. In 2017 31st International Conference on Advanced Information Networking and Applications Workshops (WAINA) (pp. 680-685). IEEE.
[c6] E. Fusella & A. Cilardo (2016, March). PhoNoCMap: an application mapping tool for photonic networks-on-chip. In 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 289-292). IEEE.
[c5] E. Fusella, A. Cilardo & A. Mazzeo. (2015, September). Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip. In 2015 25th International Conference on Field Programmable Logic and Applications (FPL) (pp. 1-2). IEEE.
[c4] E. Fusella & A. Cilardo (2015, August). Crosstalk-Aware Mapping for Tile-Based Optical Network-on-Chip. In High Performance Computing and Communications (HPCC), 2015 IEEE 7th International Symposium on Cyberspace Safety and Security (CSS), 2015 IEEE 12th International Conferen on Embedded Software and Systems (ICESS), 2015 IEEE 17th International Conference on (pp. 1139-1142). IEEE.
[c3] E. Fusella, J. Flich, A. Cilardo & A. Mazzeo. (2015, January). On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs. In Exploiting Silicon Photonics for Energy-Efficient High Performance Computing (SiPhotonics), 2015 Workshop on, co-located with HiPEAC 2015 (pp. 9-16). IEEE.
[c2] A. Cilardo, E. Fusella, L. Gallo & A. Mazzeo. (2014, March). Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems. In 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1-4). IEEE.
[c1] A. Cilardo, E. Fusella, L. Gallo & A. Mazzeo. (2013, September). Automated synthesis of FPGA-based heterogeneous interconnect topologies. In 2013 23rd International Conference on Field programmable Logic and Applications (pp. 1-8). IEEE.