CAD Tools for Photonic Networks-on-Chip

The continuous growth in application performance requirements has drastically changed the scale of multiprocessor systems-on-chip (MPSoCs). Current highly parallel MPSoCs consist of tens to hundreds of cores on a single die, requiring a high-bandwidth, low-latency and energy-efficient network-on-chip (NoC). As the network scales up, traditional electronic interconnects fail in fulfilling these requirements: at the deep submicron scale, metallic interconnects are susceptible to non-negligible parasitic resistance and capacitance resulting in poor performance and energy efficiency. Silicon photonics has generated an increasing interest over the last few years for optical interconnects in integrated circuits, providing a promising answer to effectively face the power wall, today seriously limiting further technology advances. However, to realize the potential of on-chip photonic communication to the fullest, we will thus need dedicated computer-aided design tools, just like the electronic case. The research objective of this project is to design novel CAD tools for automated photonic NoC architecture exploration and synthesis. In that respect, PhoNoCMap, our mapping tool for photonic networks-on-chip is now available for download.

MANGO: exploring Manycore Architectures for Next-GeneratiOn HPC systems

The performance/power efficiency wall poses the major challenge faced nowadays by HPC. Looking straight at the heart of the problem, the hurdle to the full exploitation of today computing technologies ultimately lies in the gap between the applications' demand and the underlying computing architecture: the closer the computing system matches the structure of the application, the most efficiently the available computing power is exploited. Consequently, enabling a deeper customization of architectures to applications is the main pathway towards computation power efficiency. MANGO is a large-scale European FETHPC project exploring heterogeneous manycore architectures for HPC, with a particular focus on architectural mechanisms for Performance/Power-efficiency/time-Predictability objectives. The project, whose total budget is 5.8 Million euro, will be based on the cooperation of the Polytechnical University of Valencia, University of Naples Federico II (CeRICT), Politecnico di Milano, University of Zagreb, EPFL, Philips, Thales, PRO-DESIGN, and Eaton.

nu+

nu+ is an open-source GPU-like compute core, developed by CeRICT in the framework of the MANGO FETHPC project. The main objective of nu+ is to enable resource-efficient HPC based on special-purpose customized hardware. On top of the customized hardware core, we are also developing a nu+ compiler backend relying on the LLVM infrastructure. Furthermore, to support the hardware development, we plan to provide at a later stage of the project a full ISA emulator to be integrated in the gem5 framework. For more information please visit the nu+ website.

Alternative Topologies for Photonic Networks-on-Chip

Despite their benefits, photonic Networks-on-Chip (NoCs) are affected by insertion loss and crosstalk noise, potentially preventing the network from operating properly. By taking into account the impact of the topological choices on insertion loss and crosstalk effects, the definition of the communication architecture can achieve a higher level of network scalability and a lower power consumption. From the topological point of view, photonic NoCs usually employ 2D regular topologies such as meshes and tori. Due to their planar nature, regular topologies suffer from a high number of waveguide crossings, one of the major components causing both insertion loss and crosstalk noise. In this project, we propose a novel optical NoC, called H2ONoC, that is based on a hybrid topology in the photonic layer as a solution enabling reduced insertion loss and crosstalk effects, hence improving the network scalability, increasing the number of available wavelengths, and reducing the energy consumption.

Design automation for application-specific on-chip interconnects

On-chip interconnects provide a vital facility for highly parallel MultiProcessor Systems-on-Chip, particularly in data-intensive applications, where the choice of the underlying communication architecture, tailored on the particular application requirements, is critical to the global performance. This project proposes automated methodologies to define optimized interconnect architectures for MPSoC applications based on the analysis of their communication requirements.